September 2026 - Morello-team - lists.cheri-alliance.org

New request
by Mike Eftimakis 05 Oct '26

05 Oct '26

Dear team, We have a new request from UC Davis: I’m an Assistant Professor in Computer Science at UC Davis working in software security and programming languages. A core focus of my group is the migration of software written in unsafe languages to safe languages. This task includes securing partially migrated code, for example, C/C++ codebases that have been partially migrated to Rust. We have been exploring the selective use of CHERI-based capability hardware to secure unsafe components in a safe codebase. For a Rust codebase, this includes code written in unsafe Rust and C code invoked over foreign function interfaces. We plan to use the Morello board for research on compiler and systems support for securing such "polyglot applications". We would use Morello to prototype capability-aware compiler transformations and runtime mechanisms, evaluate their security and performance overheads on real hardware, and study how CHERI capabilities can strengthen isolation and memory safety in existing software systems. The board would primarily support academic research and student research projects at UC Davis. I had a chat with the guy and they jointly work with Bloomberg research, so there is also additional visibility on this side. What do you think? Thanks! –– Mike Eftimakis – Founding director CHERI Alliance mike.eftimakis(a)cheri-alliance.org <mailto:mike.eftimakis@cheri-alliance.org> Web: cheri-alliance.org <http://cheri-alliance.org/>

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New request
by dan.sullivan＠cheri-alliance.org 15 Sep '26

15 Sep '26

Dear all, Please find below a new request for a Morello board: ----- Hi! I am Adriaan Jacobs (https://adriaanjacobs.github.io/) from the DistriNet research group (KU Leuven) in Ghent, Belgium, working under prof. Stijn Volckaert (https://stijn-volckaert.github.io/personal/). Our research generally focuses on exploit mitigation and compartmentalization, often using "legacy"/"already available" mechanisms rather than a capability-first processor redesign like CHERI. However, over the last few years, we have repeatedly been interested in evaluating CHERI hardware as well. At this moment, we have two ongoing projects that could benefit greatly from physical access to real CHERI hardware: 1. We are developing new "availability"/"software resilience" mechanisms, specifically for CHERI, which focus on minimizing the _power drain_ that denial-of-service attacks can cause for energy-constrained devices (such as pacemakers). For this project, we would like to perform power measurements on a real chip, since estimations in FPGAs and other platforms are not as accurate. 2. In another research line, we have been developing custom processor extensions to mitigate Spectre attacks. These can generally be regarded as a "probabilistic" capability implementation (far less strong than CHERI, but with legacy binary compatibility), and we would like to compare the speculative security guarantees in detail. Morello would by far be the easiest available platform to perform these experiments on, and perhaps also the only realistic option. We are happy to provide additional details about these projects if desired. In the past, we have repeatedly collaborated with Merve Gülmez and Thomas Nymann from Ericsson (CHERI Alliance member), and they put us in touch with Mike Eftemakis, who was kind enough to add myself and Stijn to the CHERI Alliance organization (KUL's participation was organized by Dominique Devriese) and to encourage us to apply for a Morello board. We hope that our motivation suffices to procure one, if there is still enough supply. If so, we can coordinate shipping and conditions on your terms. Kind regards, Adriaan ------ Please let me know your decision. Kind regards, Dan Sullivan Project & Community Coordinator CHERI Alliance cheri-alliance.org<http://www.cheri-alliance.org/> My working days are Monday to Wednesday

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New request
by Mike Eftimakis 08 Sep '26

08 Sep '26

Dear all, Please find below a new request for a Morello board: I would like to request an Arm Morello development board on behalf of the University of Edinburgh. Following discussions with George Neville-Neil regarding our compiler and systems research, we aim to use Morello as a hardware oracle for validating capability-aware memory models and optimising secure memory allocators. Our research focuses on compiler verification, memory safety, and systems efficiency: - Hardware Oracle for MLIR/LLVM Memory Models: We are building differential testing and fuzzing pipelines to validate memory model lowerings within MLIR and LLVM. Morello will serve as the ground-truth hardware oracle to detect subtle miscompilations, spatial/temporal safety violations, and bounds errors. - Capability-Aware Memory Allocation: Building on our prior work optimising memory allocators (GreenMalloc), we are expanding toward low-level OS, heterogeneous, and capability-hardened allocation architectures targeting CHERI. - Further development on previous work on testing system simulators (SearchSys), we are looking to continue our previous work which focused primarily on ArmV8 simulation in the Gem5 system to more niche simulation environments, guided by better and more deep introspection. This aims to further improve the CHERI ecosystem in the following ways: - Toolchain Robustness: Discovering and diagnosing edge cases in CHERI-targeting compiler backends. - Open-Source Artifacts: All fuzzing harnesses, MLIR test suites, and allocator evaluations will be published open-source for the CHERI and LLVM communities. - Disseminating findings through systems/compiler conferences, highlighting the practical security benefits of CHERI hardware. Why Morello Hardware is Essential: - Fuzzing & Execution Scale: Large-scale compiler fuzzing requires millions of iterations. QEMU’s emulation overhead is a prohibitive bottleneck for high-throughput differential testing. - Full 64-Bit Application Scale: Sonata targets 32-bit embedded RISC-V microcontrollers, whereas our MLIR lowerings, compiler optimisations, and allocator workloads target 64-bit, multi-core application processors. - Bare-Metal Concurrency & Microarchitecture: Accurate validation of multi-core memory models, hardware tag propagation, and capability faults requires physical silicon execution rather than idealised emulation. Happy to get your feedback. Thanks and best regards, –– Mike Eftimakis – Founding director CHERI Alliance mike.eftimakis(a)cheri-alliance.org <mailto:mike.eftimakis@cheri-alliance.org> Web: cheri-alliance.org <http://cheri-alliance.org/>

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