Dear all,
Please find below a new request for a Morello board:
I would like to request an Arm Morello development board on behalf of the University of Edinburgh. Following discussions with George Neville-Neil regarding our compiler and systems research, we aim to use Morello as a hardware oracle for validating capability-aware memory models and optimising secure memory allocators. Our research focuses on compiler verification, memory safety, and systems efficiency:
- Hardware Oracle for MLIR/LLVM Memory Models: We are building differential testing and fuzzing pipelines to validate memory model lowerings within MLIR and LLVM. Morello will serve as the ground-truth hardware oracle to detect subtle miscompilations, spatial/temporal safety violations, and bounds errors.
- Capability-Aware Memory Allocation: Building on our prior work optimising memory allocators (GreenMalloc), we are expanding toward low-level OS, heterogeneous, and capability-hardened allocation architectures targeting CHERI.
- Further development on previous work on testing system simulators (SearchSys), we are looking to continue our previous work which focused primarily on ArmV8 simulation in the Gem5 system to more niche simulation environments, guided by better and more deep introspection.
This aims to further improve the CHERI ecosystem in the following ways:
- Toolchain Robustness: Discovering and diagnosing edge cases in CHERI-targeting compiler backends.
- Open-Source Artifacts: All fuzzing harnesses, MLIR test suites, and allocator evaluations will be published open-source for the CHERI and LLVM communities.
- Disseminating findings through systems/compiler conferences, highlighting the practical security benefits of CHERI hardware.
Why Morello Hardware is Essential:
- Fuzzing & Execution Scale: Large-scale compiler fuzzing requires millions of iterations. QEMU’s emulation overhead is a prohibitive bottleneck for high-throughput differential testing.
- Full 64-Bit Application Scale: Sonata targets 32-bit embedded RISC-V microcontrollers, whereas our MLIR lowerings, compiler optimisations, and allocator workloads target 64-bit, multi-core application processors.
- Bare-Metal Concurrency & Microarchitecture: Accurate validation of multi-core memory models, hardware tag propagation, and capability faults requires physical silicon execution rather than idealised emulation.
Happy to get your feedback.
Thanks and best regards,
––
Mike Eftimakis – Founding director
CHERI Alliance
mike.eftimakis(a)cheri-alliance.org <mailto:mike.eftimakis@cheri-alliance.org>
Web: cheri-alliance.org <http://cheri-alliance.org/>
Dear all,
We have a new request for a Morello board:
Sensor IT has just been awarded funding by Innovate UK for a project in Advanced Connectivity Solutions. As part of this grant, Sensor IT will implement Open RAN software onto the Morello Board, which includes both porting standard packages (Linux) that may be required as part of the implementation, as well as migrating Open RAN packages such as srsRAN and Open5GS. The team is geographically dispersed, with some of them based in London and others further up north. Even though once we settle on the final architecture one board shared through a VPN line may be enough, if it was possible to have access to another one that will be shipped to our other, north-based, team of resources would make the development much more feasible, hence this request.
This is a concrete project. They already have a board, but would like a second one for their other team.
Are you happy to support this?
Thanks!
––
Mike Eftimakis – Founding director
CHERI Alliance
mike.eftimakis(a)cheri-alliance.org <mailto:mike.eftimakis@cheri-alliance.org>
Web: cheri-alliance.org <http://cheri-alliance.org/>
